The present invention relates generally to a magnetically coupled Gate Driver for providing transformer isolated high and low control and gate drive to Power Devices, such as IGBT or MOSFET, using a single transformer and no interface opto-couplers for the Gating or Fault signals. More particularly, the Gate Driver of the present invention may be hermetically sealed and integrates high and low direct current power supplies, gating control, gate drive and Power Device diagnostics into a sealed Integrated Power Device Package. This eliminates the need for opto-coupler or I/O (input/output) pin connections or wires through the wall of the device package which would increase the complexity and cost of achieving a hermetic Power Device. The magnetic coupling method described in this invention facilitates integration of a Gate Driver with a High Power Device Module and simplifies hermetic sealing of both from ambient environment by eliminating the number of control interfaces/pins to and from the Gate Driver in hermetic and non hermetic applications.
In typical Power Device applications, High Power Device Modules (HPSM), such as Insulated Gate Bipolar Transistors (IGBT) or Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFET), are controlled via commercial off-the-shelf (COTS) Gate Drivers or custom discrete designs. A typical COTS driver is described in, for example, the TD350 advanced MOSFET/IGBT Driver brochure, Siegbert Troeger, Silica, Germany. The TD350 brochure shows a 14-pin package, the main advantages of COTS driver chips are simplified design, reduce cost and area.
U.S. Pat. No. 6,851,077 describes a monolithic integrated quadruple-Gate Driver having a three-phase bridge circuit for a direct gate control and monitoring of several semiconductor switches in a converter, wherein an example of the driver described shows a 28-pin small outline package.
HPSMs, with or without Integrated Gate Drivers, are frequently used in a variety of terrestrial and non-terrestrial operating conditions and are subject to degradation and failure from atmospheric and non-atmospheric contaminants. To maintain operational integrity, HPSMs must be sealed against such contaminants. The process of sealing an HPSM is difficult and expensive, requiring all pin connections into and out of the HPSM to be prepared and sealed prior to use. In HPSMs with Integrated Gate Drivers, reducing or eliminating the number of electrical connections in and out of the HPSM is crucial in achieving a reliable, hermetically sealed, low cost HPSM. As shown in the TD350 brochure and in U.S. Pat. No. 6,851,077, typical Gate Drivers have multiple connections both into and out of the module, thereby sealing each unit before putting a unit into operation makes each unit more expensive. Moreover, hermetically sealing each unit to keep out humidity or for use under reduced atmospheric pressure or in a vacuum, such as outer space, is significantly more difficult and expensive.
U.S. Pat. No. 5,142,432 shows how one can transfer V+ power supply plus gating and/or PHM signal through a single transformer. However, the '432 patent does not show how V− for turn off is derived nor does it propose or discuss how to realize a hermetic Gate Driver plus Power Device.
The TD350 brochure shows that the TD350 Gate Driver utilizes a single transformer. U.S. Pat. No. 5,900,683 describes an isolated Gate Driver having a plurality of high frequency pulse transformers. The isolated Gate Driver described in U.S. Pat. No. 5,900,683, includes a primary circuit having a voltage source of a first voltage potential wherein the primary circuit constantly switches the voltage source to generate first and second load signals based on the control signals. The first load signal modulates at a first frequency for enabling the transistors and the second load signal modulates at a second frequency, different from the first frequency, for disabling the transistors. Typically, COTS Gate Drivers utilize one or two high frequency transformers and additional complex circuitry to provide a positive high power voltage to bias the Power Device conductive and an isolated negative low power voltage as a guard voltage to bias the Power Device nonconductive.
Although typical COTS Gate Drivers have generally incorporated various Gate Driver and device diagnostics and other Prognostics Health Monitoring (PHM) as a feature, such features require additional I/O circuitry and methods of signal isolation. For example, U.S. Pat. No. 5,142,432 describes an isolated Gate Driver having a single transformer, which electrically isolates logic level and power circuits of a power transistor drive circuit and also detects power circuit fault conditions at the isolated, logic level side of the circuit. When a fault condition exists, a current increase results in a voltage increase at output of drivers, which apply the gating signals to the primary winding of the isolation transformer. Voltage at the output of the drivers is periodically sensed to determine if it exceeds a threshold level. When the threshold level is exceeded, a fault signal indicates to the controller that a fault condition has occurred. In general, implementation of such features typically requires additional components, additional pin connections and increased board space, thus adding to cost and weight and potential unreliability of the Gate Driver. Moreover, any additional I/O pin connections make the unit correspondingly difficult and expensive to seal. As one can easily understand, an application environment requiring a hermetically sealed unit having onboard diagnostics makes the cost to hermetically sealing the unit significant.
As stated above, U.S. Pat. No. 5,900,683 describes an isolated Gate Driver having a plurality of high frequency pulse transformers. U.S. Pat. No. 6,851,077 further describes hybrid IGBT control circuits with galvanic separation of the primary side from the secondary side by means of opto-couplers, a fast opto-coupler is used for the signal path, and a usually slower second opto-coupler is used for error messages. Although U.S. Pat. No. 6,851,077 describes the advantage of transformers versus opto-couplers, the monolithic integrated quadruple-Gate Driver described requires potential separation for the three-phase bridge circuits which is achieved by means of opto-couplers.
Generally, typical Gate Drivers may use one or more transformers and optionally use one or more opto-couplers. For example, a typical implementation uses a single transformer for power and two opto-couplers, one opto-coupler for the gating signal and one opto-coupler for detecting Gate Driver fault. Such implementation is illustrated in FIG. 1.
With regard to FIG. 1, there is shown a block diagram/schematic representation of a Gate Driver 100 with one transformer TR1 and two opto-couplers, U1A and U1B. Symmetric square-wave power may provide the gating power to the Gate Driver 100 through transformer TR1, rectifier diodes D1, D2 and D3 and filtering capacitors C1 and C2 to generate V+ and V− for the Gate Driver 100. A UV Detection block 102 may monitor the V+ and V− voltages and generate a fault signal 104 if either V+ or V− is above or below certain limits.
A de-saturation detection block 106 may compare the state of the Power Device Q3 to the commanded state. For example, when the Power Device is commanded ON, Voltage 108 (with respect to the COMMON REF, 122) should be less than 3V. In the event of de-saturation, this Voltage 108 will be many times higher than 3V. When this condition occurs the De-Saturation Detection generates a fault signal by changing the state of signal 120. The Fault Signal Processing block receives this signal and generally performs two functions, a) sends a signal to the Gating Signal Processing block so that the Power Device is commanded OFF and b) sends a fault signal through the U1B opto-coupler for processing outside the Gate Driver, Fault Signal 112.
In general, the fault signal processing block 110 may process one or more generated fault signals and generate a common fault signal 112 sent outside the Gate Driver 100 through opto-coupler U1B and at the same time change the state of the Gate Driver output in a manner that protects the Power Device Q3.
A gating signal processing block 114 may determine the state of the Gate Driver output based on the gating signal 116 and the fault signal processing block 110. MOSFETS Q1 and Q2 are the final drive stages of the Gate Driver 100, when Q1 is conducting, V+ is applied to the gate of Power Device Q3, when Q2 is conducting, V− is applied to the Gate of Power Device Q3.
The gating signal block 116 generates an ON/OFF command outside the Gate Driver 100, typically the ON/OFF command is a square two-level pulse where voltage level 1 is a command to turn the Gate Driver 100 ON and voltage level 2 is a command to turn the Gate Driver 100 OFF. It's important to note that the Gating and Fault Signals, 116 and 112 respectively, are outside the Gate Driver 100 and are floating with respect to the Gate Driver 100, hence the need of the opto-couplers, U1A and U1B, to maintain isolation.
The Fault Signal Processing block 110 receives one or more fault signals, in this case two fault signals, 104 from the UV Detection block and 120 from the De-saturation Detection block, and typically generates a single fault signal that turns the Power Device OFF and signals outside the Gate Driver that a fault has occurred. The fault signal is typically a two-level signal, where voltage level 1 represents the normal state of the Gate Driver 100 and voltage level 2 represents a fault state.
Other implementations have been reported in prior art which use no opto-couplers and two transformers, one transformer for positive voltage (V+) and turn-on (ON gating status) signal and one transformer for negative voltage (V−) and turn-off (OFF gating status) signal. A possible implementation may use no opto-couplers and two transformers; i.e., one transformer for power and one transformer for the gating signal with no diagnostics. Another possible implementation may use one opto-coupler and two transformers, one transformer for power, one transformer for the gating signal and the opto-coupler for signaling a Gate Driver fault.
As can be seen, there remains a need for a method for providing an isolated power supply, gating signal and detecting Gate Driver fault status or other status, to and from a Power Device with a Gate Driver that is relatively simple, inexpensive and has the ability to be easily hermetically sealed when integrated with the Power Device.